vhdl-testbench-statements

vhdl-testbench-statements is a variable defined in `vhdl-mode.el'.
Its value is

"  -- clock generation\n  Clk <= not Clk after 10 ns;\n\n  -- waveform generation\n  WaveGen_Proc: process\n  begin\n    -- insert signal assignments here\n\n    wait until Clk = '1';\n  end process WaveGen_Proc;\n"

Documentation:
String or file to be inserted in the testbench statement part.
If the string specifies an existing file name, the contents of the file is
inserted, otherwise the string itself is inserted in the testbench
architecture before the END keyword.
Type `C-j' for newlines.

You can customize this variable.