vhdl-testbench-declarations

vhdl-testbench-declarations is a variable defined in `vhdl-mode.el'.
Its value is

"  -- clock
  signal Clk : std_logic := '1';
"

Documentation:
String or file to be inserted in the testbench declarative part.
If the string specifies an existing file name, the contents of the file is
inserted, otherwise the string itself is inserted in the testbench
architecture before the BEGIN keyword.
Type `C-j' for newlines.

You can customize this variable.