vhdl-model-alist

vhdl-model-alist is a variable defined in `vhdl-mode.el'.
Its value is

(("Example Model" " : process (, )\nbegin  -- process \n  if  = '0' then  -- asynchronous reset (active low)\n    \n  elsif 'event and  = '1' then  -- rising clock edge\n    if  = '1' then  -- synchronous load\n\n    end if;\n  end if;\nend process ;" "e" ""))

Documentation:
List of user models.
VHDL models (templates) can be specified by the user in this list. They can be
invoked from the menu, through key bindings (`C-c C-m ...'), or by keyword
electrification (i.e. overriding existing or creating new keywords, see
option `vhdl-electric-keywords').
Name : name of model (string of words and spaces)
String : string or name of file to be inserted as model (newline: `C-j')
Key Binding: key binding to invoke model, added to prefix `C-c C-m'
(must be in double-quotes, examples: "i", "\C-p", "\M-s")
Keyword : keyword to invoke model

The models can contain prompts to be queried. A prompt is of the form "<...>".
A prompt that appears several times is queried once and replaced throughout
the model. Special prompts are:
: name specified in `vhdl-clock-name' (if not empty)
: name specified in `vhdl-reset-name' (if not empty)
: final cursor position
File header prompts (see variable `vhdl-file-header') are automatically
replaced, so that user models can also be used to insert different types of
headers.

If the string specifies an existing file name, the contents of the file is
inserted, otherwise the string itself is inserted.
The code within the models should be correctly indented.
Type `C-j' for newlines.

NOTE: Activate the new setting in a VHDL buffer by using the menu entry
"Activate Options".

You can customize this variable.