vhdl-insert-empty-lines

vhdl-insert-empty-lines is a variable defined in `vhdl-mode.el'.
Its value is

unit

Documentation:
Specifies whether to insert empty lines in some templates.
This improves readability of code. Empty lines are inserted in:
None : no constructs
Design units only: entities, architectures, configurations, packages only
All constructs : also all constructs with BEGIN...END parts

Replaces option `vhdl-additional-empty-lines'.

You can customize this variable.