verilog-zero-indent-re
verilog-zero-indent-re is a variable defined in `verilog-mode.el'.
Its value is "\\<\\(c\\(?:lass\\|onfig\\)\\|interface\\|m\\(?:\\(?:acrom\\)?odule\\)\\|p\\(?:ackage\\|r\\(?:imitive\\|ogram\\)\\)\\)\\>\\|\\<\\(end\\(?:c\\(?:lass\\|onfig\\)\\|interface\\|module\\|p\\(?:ackage\\|r\\(?:imitive\\|ogram\\)\\)\\)\\)\\>"
- This variable may be risky if used as a file-local variable.