verilog-uvm-end-re

verilog-uvm-end-re is a variable defined in `verilog-mode.el'.
Its value is

"\\(?:`uvm_\\(?:\\(?:component\\|field\\|object\\|sequencer?\\)_utils_end\\)\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.