verilog-uvm-begin-re

verilog-uvm-begin-re is a variable defined in `verilog-mode.el'.
Its value is

"\\(?:`uvm_\\(?:\\(?:component\\(?:_param\\)?\\|field\\|object\\(?:_param\\)?\\|sequencer?\\)_utils_begin\\)\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.