verilog-template-map

verilog-template-map is a variable defined in `verilog-mode.el'.
Its value is shown below.

• This variable may be risky if used as a file-local variable.

Documentation:
Keymap used in Verilog mode for smart template operations.

Value:

(keymap
 (68 . verilog-sk-define-signal)
 (82 . verilog-sk-reg)
 (87 . verilog-sk-wire)
 (85 . verilog-sk-uvm-component)
 (61 . verilog-sk-inout)
 (83 . verilog-sk-state-machine)
 (79 . verilog-sk-output)
 (73 . verilog-sk-input)
 (70 . verilog-sk-function)
 (65 . verilog-sk-assign)
 (47 . verilog-sk-comment)
 (58 . verilog-sk-else-if)
 (63 . verilog-sk-if)
 (122 . verilog-sk-casez)
 (120 . verilog-sk-casex)
 (119 . verilog-sk-while)
 (117 . verilog-sk-uvm-object)
 (116 . verilog-sk-task)
 (115 . verilog-sk-specify)
 (114 . verilog-sk-repeat)
 (112 . verilog-sk-primitive)
 (111 . verilog-sk-ovm-class)
 (109 . verilog-sk-module)
 (106 . verilog-sk-fork)
 (105 . verilog-sk-initial)
 (104 . verilog-sk-header)
 (103 . verilog-sk-generate)
 (102 . verilog-sk-for)
 (99 . verilog-sk-case)
 (98 . verilog-sk-begin)
 (97 . verilog-sk-always))