verilog-simulator

verilog-simulator is a variable defined in `verilog-mode.el'.
Its value is

"echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"

Documentation:
Program and arguments to use to interpret Verilog source.
Depending on the `verilog-set-compile-command', this may be invoked when
you type M-x compile. When the compile completes, C-x ` will take
you to the next lint error.

You can customize this variable.