verilog-preprocessor-re

verilog-preprocessor-re is a variable defined in `verilog-mode.el'.
Its value is

"\\(?:\\<\\(`\\(?:__\\(?:\\(?:FIL\\|LIN\\)E__\\)\\|celldefine\\|e\\(?:lse\\|nd\\(?:_keywords\\|celldefine\\|if\\)\\)\\|nounconnected_drive\\|resetall\\|un\\(?:connected_drive\\|defineall\\)\\)\\)\\>\\)\\|\\(?:\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-\\)\\|\\(?:\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]\\)\\|\\(?:\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)\\)\\|\\(?:\\<\\(`pragma\\)\\>\\s-+.+$\\)\\|\\(?:\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s\\)\\|\\(?:\\<\\(`define\\|`if\\)\\>\\s-+\\(.*\\(?:\n.*\\)*?\\)\\(?:\n\\s-*\n\\|\\'\\)\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.