verilog-ovm-statement-re

verilog-ovm-statement-re is a variable defined in `verilog-mode.el'.
Its value is

"\\(?:`\\(?:DUT_ERROR\\|MESSAGE\\|dut_error\\|message\\|ovm_\\(?:analysis_imp_decl\\|blocking_\\(?:\\(?:get\\(?:_peek\\)?\\|master\\|p\\(?:eek\\|ut\\)\\|slave\\|transport\\)_imp_decl\\)\\|c\\(?:omponent_\\(?:registry\\(?:_param\\)?\\|utils\\)\\|reate\\(?:_seq\\)?\\)\\|d\\(?:eclare_sequence_lib\\|o\\(?:_\\(?:seq\\(?:_with\\)?\\|with\\)\\)?\\)\\|error\\|f\\(?:atal\\|i\\(?:eld_\\(?:a\\(?:a_\\(?:int_\\(?:byte\\(?:_unsigned\\)?\\|int\\(?:_unsigned\\|eger\\(?:_unsigned\\)?\\)?\\|key\\|longint\\(?:_unsigned\\)?\\|s\\(?:hortint\\(?:_unsigned\\)?\\|tring\\)\\)\\|object_\\(?:int\\|string\\)\\|string_\\(?:int\\|string\\)\\)\\|rray_\\(?:int\\|object\\|string\\)\\)\\|e\\(?:num\\|vent\\)\\|int\\|object\\|queue_\\(?:int\\|object\\|string\\)\\|s\\(?:array_int\\|tring\\)\\|utils\\)\\|le\\)\\)\\|get_\\(?:\\(?:peek_\\)?imp_decl\\)\\|info[1-4]?\\|line\\|m\\(?:\\(?:aster_imp_dec\\|sg_detai\\)l\\)\\|non\\(?:\\(?:_blocking_transport\\|blocking_\\(?:get\\(?:_peek\\)?\\|master\\|p\\(?:eek\\|ut\\)\\|slave\\)\\)_imp_decl\\)\\|object_\\(?:registry\\(?:_param\\)?\\|utils\\)\\|p\\(?:eek_imp_decl\\|hase_\\(?:\\(?:func\\|task\\)_decl\\)\\|rint_\\(?:a\\(?:a_\\(?:int_object\\|string_\\(?:int\\|object\\|string\\)\\)\\|rray_\\(?:int\\|object\\|string\\)\\)\\|object_queue\\|queue_int\\|string_queue\\)\\|ut_imp_decl\\)\\|rand_send\\(?:_with\\)?\\|s\\(?:e\\(?:nd\\|quence_utils\\)\\|lave_imp_decl\\)\\|transport_imp_decl\\|update_sequence_lib\\(?:_and_item\\)?\\|warning\\)\\|static_\\(?:dut_error\\|message\\)\\)\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.