verilog-optional-signed-range-re

verilog-optional-signed-range-re is a variable defined in `verilog-mode.el'.
Its value is

"\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\\\s-*\\)?\\(\\(\\[[^]]*\\]\\s-*\\)+\\)?"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.