verilog-no-indent-begin-re

verilog-no-indent-begin-re is a variable defined in `verilog-mode.el'.
Its value is

"\\<\\(always\\(?:_\\(?:comb\\|ff\\|latch\\)\\)?\\|do\\|else\\|f\\(?:inal\\|or\\(?:e\\(?:ach\\|ver\\)\\)?\\)\\|i\\(?:f\\|nitial\\)\\|repeat\\|while\\)\\>"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.