verilog-nameable-item-re

verilog-nameable-item-re is a variable defined in `verilog-mode.el'.
Its value is

"\\<\\(begin\\|end\\(?:c\\(?:ase\\|hecker\\|l\\(?:ass\\|ocking\\)\\|onfig\\)\\|function\\|g\\(?:enerate\\|roup\\)\\|interface\\|module\\|p\\(?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\\)\\)\\)\\|s\\(?:equence\\|pecify\\)\\|ta\\(?:ble\\|sk\\)\\)?\\|fork\\|join\\(?:_\\(?:any\\|none\\)\\)?\\)\\>"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.