verilog-mode-abbrev-table

verilog-mode-abbrev-table is a variable defined in `verilog-mode.el'.
Its value is

[## 0 task 0 0 0 0 0 input 0 0 primitive if 0 initial 0 0 0 module 0 0 0 specify 0 0 0 while begin 0 0 0 0 0 0 fork 0 for 0 wire 0 else\ if casex output casez 0 0 reg inout assign 0 generate 0 0 0 0 0 0 class 0]

Documentation:
Abbrev table in use in Verilog-mode buffers.