verilog-indent-re

verilog-indent-re is a variable defined in `verilog-mode.el'.
Its value is

"\\<\\(`\\(?:case\\|def\\(?:ault\\|ine\\)\\|e\\(?:ls\\(?:e\\|if\\)\\|nd\\(?:for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(?:mat\\)?\\|i\\(?:f\\(?:n?def\\)?\\|nclude\\)\\|let\\|ovm_\\(?:component_\\(?:param_utils_begin\\|utils_\\(?:begin\\|end\\)\\)\\|field_utils_\\(?:begin\\|end\\)\\|object_\\(?:param_utils_begin\\|utils_\\(?:begin\\|end\\)\\)\\|sequence\\(?:_utils_\\(?:begin\\|end\\)\\|r_utils_\\(?:begin\\|end\\)\\)\\)\\|protect\\|switch\\|time\\(?:_?scale\\)\\|u\\(?:ndef\\|vm_\\(?:component_\\(?:param_utils_begin\\|utils_\\(?:begin\\|end\\)\\)\\|field_utils_\\(?:begin\\|end\\)\\|object_\\(?:param_utils_begin\\|utils_\\(?:begin\\|end\\)\\)\\|sequence\\(?:_utils_\\(?:begin\\|end\\)\\|r_utils_\\(?:begin\\|end\\)\\)\\)\\)\\|vmm_\\(?:data_member_\\(?:begin\\|end\\)\\|env_member_\\(?:begin\\|end\\)\\|s\\(?:cenario_member_\\(?:begin\\|end\\)\\|ubenv_member_\\(?:begin\\|end\\)\\)\\|xactor_member_\\(?:begin\\|end\\)\\)\\|while\\)\\|always\\(?:_\\(?:comb\\|ff\\|latch\\)\\)?\\|begin\\|c\\(?:ase[xz]?\\|l\\(?:ass\\|ocking\\)\\|o\\(?:nfig\\|vergroup\\)\\)\\|end\\(?:c\\(?:ase\\|l\\(?:ass\\|ocking\\)\\|onfig\\)\\|function\\|g\\(?:enerate\\|roup\\)\\|interface\\|module\\|p\\(?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\\)\\)\\)\\|s\\(?:equence\\|pecify\\)\\|ta\\(?:ble\\|sk\\)\\)?\\|f\\(?:inal\\|ork\\|unction\\)\\|generate\\|in\\(?:itial\\|terface\\)\\|join\\(?:_\\(?:any\\|none\\)\\)?\\|m\\(?:\\(?:acrom\\)?odule\\)\\|p\\(?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\\)\\)\\)\\|rand\\(?:\\(?:cas\\|sequenc\\)e\\)\\|s\\(?:equence\\|pecify\\)\\|ta\\(?:ble\\|sk\\)\\|virtual\\|{\\)\\>"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.