verilog-indent-level-module

verilog-indent-level-module is a variable defined in `verilog-mode.el'.
Its value is

3

• This variable is safe as a file local variable if its value
  satisfies the predicate `integerp'.

Documentation:
Indentation of Module level Verilog statements (eg always, initial).
Set to 0 to get initial and always statements lined up on the left side of
your screen.

You can customize this variable.