verilog-indent-declaration-macros

verilog-indent-declaration-macros is a variable defined in `verilog-mode.el'.
Its value is

nil

• This variable is safe as a file local variable if its value
  satisfies the predicate `verilog-booleanp'.

Documentation:
How to treat macro expansions in a declaration.
If nil, indent as:
input [31:0] a;
input `CP;
output c;
If non nil, treat as:
input [31:0] a;
input `CP ;
output c;

You can customize this variable.