verilog-ends-re

verilog-ends-re is a variable defined in `verilog-mode.el'.
Its value is

"\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\<`vmm_data_member_end\\>\\)\\|\\(\\<`vmm_env_member_end\\>\\)\\|\\(\\<`vmm_scenario_member_end\\>\\)\\|\\(\\<`vmm_subenv_member_end\\>\\)\\|\\(\\<`vmm_xactor_member_end\\>\\)\\|\\(\\<`ovm_component_utils_end\\>\\)\\|\\(\\<`ovm_field_utils_end\\>\\)\\|\\(\\<`ovm_object_utils_end\\>\\)\\|\\(\\<`ovm_sequence_utils_end\\>\\)\\|\\(\\<`ovm_sequencer_utils_end\\>\\)\\(\\<`uvm_component_utils_end\\>\\)\\|\\(\\<`uvm_field_utils_end\\>\\)\\|\\(\\<`uvm_object_utils_end\\>\\)\\|\\(\\<`uvm_sequence_utils_end\\>\\)\\|\\(\\<`uvm_sequencer_utils_end\\>\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.