verilog-directive-re

verilog-directive-re is a variable defined in `verilog-mode.el'.
Its value is

"\\<\\(`\\(?:case\\|def\\(?:ault\\|ine\\)\\|e\\(?:ls\\(?:e\\|if\\)\\|nd\\(?:for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(?:mat\\)?\\|i\\(?:f\\(?:n?def\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(?:_?scale\\)\\|undef\\|while\\)\\)\\>"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.