verilog-directive-nest-re

verilog-directive-nest-re is a variable defined in `verilog-mode.el'.
Its value is

"\\(`else\\>\\)\\|\\(`endif\\>\\)\\|\\(`if\\>\\)\\|\\(`ifdef\\>\\)\\|\\(`ifndef\\>\\)\\|\\(`elsif\\>\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.