verilog-delay-re

verilog-delay-re is a variable defined in `verilog-mode.el'.
Its value is

"#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.