verilog-declaration-re-1-macro

verilog-declaration-re-1-macro is a variable defined in `verilog-mode.el'.
Its value is

"^\\s-*\\(\\<\\(const\\|in\\(?:[op]ut\\)\\|local\\(?:param\\)?\\|output\\|p\\(?:arameter\\|rotected\\)\\|ref\\|static\\|typedef\\|var\\)\\>\\s-*\\)?\\<\\(b\\(?:it\\|yte\\)\\|chandle\\|e\\(?:num\\|vent\\)\\|genvar\\|in\\(?:out\\|put\\|t\\(?:eger\\)?\\)\\|lo\\(?:gic\\|ngint\\)\\|mailbox\\|output\\|re\\(?:al\\(?:time\\)?\\|g\\)\\|s\\(?:emaphore\\|hort\\(?:int\\|real\\)\\|tr\\(?:ing\\|uct\\)\\|upply[01]\\)\\|t\\(?:ime\\|ri\\(?:and\\|or\\|reg\\|[01]\\)?\\)\\|u\\(?:nion\\|wire\\)\\|virtual\\|w\\(?:and\\|ire\\|or\\)\\)\\>\\s-*\\(\\(\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\\\s-*\\)?\\(\\(\\[[^]]*\\]\\s-*\\)+\\)?\\)\\|\\(#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)\\)\\|\\(`\\sw+\\)\\)?"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.