verilog-declaration-core-re

verilog-declaration-core-re is a variable defined in `verilog-mode.el'.
Its value is

"\\<\\(b\\(?:it\\|yte\\)\\|chandle\\|e\\(?:num\\|vent\\)\\|genvar\\|in\\(?:out\\|put\\|t\\(?:eger\\)?\\)\\|lo\\(?:gic\\|ngint\\)\\|mailbox\\|output\\|re\\(?:al\\(?:time\\)?\\|g\\)\\|s\\(?:emaphore\\|hort\\(?:int\\|real\\)\\|tr\\(?:ing\\|uct\\)\\|upply[01]\\)\\|t\\(?:ime\\|ri\\(?:and\\|or\\|reg\\|[01]\\)?\\)\\|u\\(?:nion\\|wire\\)\\|virtual\\|w\\(?:and\\|ire\\|or\\)\\)\\>"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.