verilog-cpp-level-re

verilog-cpp-level-re is a variable defined in `verilog-mode.el'.
Its value is

"\\<\\(end\\(?:class\\|interface\\|module\\|p\\(?:ackage\\|r\\(?:imitive\\|ogram\\)\\)\\)\\)\\>"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.