verilog-complete-reg

verilog-complete-reg is a variable defined in `verilog-mode.el'.
Its value is

"\\(\\(\\\\s-+\\)?virtual\\s-+\\|\\\\|\\\\)\\)\\|\\(\\(\\\\s-+\\)*\\(\\\\|\\\\|\\\\)\\)\\|\\(\\(\\\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-+=\\s-+\\)?\\(function\\>\\|task\\>\\)\\)\\|\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)\\|\\(\\<\\(a\\(?:lways\\(?:_\\(?:comb\\|ff\\|latch\\)\\)?\\|ss\\(?:ert\\|ign\\)\\)\\|constraint\\|do\\|else\\|f\\(?:inal\\|or\\(?:e\\(?:ach\\|ver\\)\\)?\\)\\|i\\(?:f\\|mport\\|nitial\\)\\|localparam\\|m\\(?:\\(?:acrom\\)?odule\\)\\|parameter\\|r\\(?:andcase\\|epeat\\)\\|while\\)\\>\\)"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.