verilog-case-keywords

verilog-case-keywords is a variable defined in `verilog-mode.el'.
Its value is

("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")

Documentation:
Keywords to complete when at first word of a line in case scope.
(begin, if, then, else, for, fork...)
The procedures and variables defined within the Verilog program
will be completed at runtime and should not be added to this list.