verilog-beg-block-re

verilog-beg-block-re is a variable defined in `verilog-mode.el'.
Its value is

"\\<\\(`\\(?:\\(?:ovm_\\(?:\\(?:component\\(?:_param\\)?\\|field\\|object\\(?:_param\\)?\\|sequencer?\\)_utils\\)\\|uvm_\\(?:\\(?:component\\(?:_param\\)?\\|field\\|object\\(?:_param\\)?\\|sequencer?\\)_utils\\)\\|vmm_\\(?:\\(?:data\\|env\\|s\\(?:cenario\\|ubenv\\)\\|xactor\\)_member\\)\\)_begin\\)\\|begin\\|c\\(?:ase[xz]?\\|locking\\)\\|f\\(?:ork\\|unction\\)\\|generate\\|property\\|randcase\\|specify\\|ta\\(?:ble\\|sk\\)\\)\\>"

• This variable may be risky if used as a file-local variable.

Documentation:
Not documented as a variable.