verilog-auto-output-ignore-regexp

verilog-auto-output-ignore-regexp is a variable defined in `verilog-mode.el'.
Its value is

nil

• This variable is safe as a file local variable if its value
  satisfies the predicate `stringp'.

Documentation:
If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
See the M-x verilog-faq for examples on using this.

You can customize this variable.