verilog-auto-inst-vector

verilog-auto-inst-vector is a variable defined in `verilog-mode.el'.
Its value is

t

• This variable is safe as a file local variable if its value
  satisfies the predicate `verilog-booleanp'.

Documentation:
Non-nil means when creating default ports with AUTOINST, use bus subscripts.
If nil, skip the subscript when it matches the entire bus as declared in
the module (AUTOWIRE signals always are subscripted, you must manually
declare the wire to have the subscripts removed.) Setting this to nil may
speed up some simulators, but is less general and harder to read, so avoid.

You can customize this variable.