verilog-auto-inst-dot-name

verilog-auto-inst-dot-name is a variable defined in `verilog-mode.el'.
Its value is

nil

• This variable is safe as a file local variable if its value
  satisfies the predicate `verilog-booleanp'.

Documentation:
Non-nil means when creating ports with AUTOINST, use .name syntax.
This will use ".port" instead of ".port(port)" when possible.
This is only legal in SystemVerilog files, and will confuse older
simulators. Setting `verilog-auto-inst-vector' to nil may also
be desirable to increase how often .name will be used.

You can customize this variable.