vhdl-template-for

vhdl-template-for is an interactive compiled Lisp function in `vhdl-mode.el'.


(vhdl-template-for)

Insert a block or component configuration if within a configuration
declaration, a configuration specification if within an architecture
declarative part (and not within a subprogram), a for-loop if within a
sequential statement part (subprogram or process), and a for-generate
otherwise.