verilog-set-compile-command

verilog-set-compile-command is an interactive compiled Lisp function in `verilog-mode.el'.


(verilog-set-compile-command)

Function to compute shell command to compile Verilog.

This reads `verilog-tool' and sets `compile-command'. This specifies the
program that executes when you type M-x compile or
M-x verilog-auto-save-compile.

By default `verilog-tool' uses a Makefile if one exists in the
current directory. If not, it is set to the `verilog-linter',
`verilog-compiler', `verilog-coverage', `verilog-preprocessor',
or `verilog-simulator' variables, as selected with the Verilog ->
"Choose Compilation Action" menu.

You should set `verilog-tool' or the other variables to the path and
arguments for your Verilog simulator. For example:
"vcs -p123 -O"
or a string like:
"(cd /tmp; surecov %s)".

In the former case, the path to the current buffer is concat'ed to the
value of `verilog-tool'; in the later, the path to the current buffer is
substituted for the %s.

Where __FLAGS__ appears in the string `verilog-current-flags'
will be substituted.

Where __FILE__ appears in the string, the variable
`buffer-file-name' of the current buffer, without the directory
portion, will be substituted.