verilog-read-sub-decls

verilog-read-sub-decls is a compiled Lisp function in `verilog-mode.el'.

(verilog-read-sub-decls)

Internally parse signals going to modules under this module.
Return an array of [ outputs inouts inputs ] signals for modules that are
instantiated in this module. For example if declare A A (.B(SIG)) and SIG
is an output, then SIG will be included in the list.

This only works on instantiations created with /*AUTOINST*/ converted by
M-x verilog-auto-inst. Otherwise, it would have to read in the whole
component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs and //
Outputs comments above subcell signals, for example:

module ModuleName (
// Outputs
.out (out),
// Inputs
.in (in));