verilog-auto

verilog-auto is an interactive compiled Lisp function in `verilog-mode.el'.


(verilog-auto &optional INJECT)

Expand AUTO statements.
Look for any /*AUTO...*/ commands in the code, as used in
instantiations or argument headers. Update the list of signals
following the /*AUTO...*/ command.

Use M-x verilog-delete-auto to remove the AUTOs.

Use M-x verilog-diff-auto to see differences in AUTO expansion.

Use M-x verilog-inject-auto to insert AUTOs for the first time.

Use M-x verilog-faq for a pointer to frequently asked questions.

For new users, we recommend setting `verilog-case-fold' to nil
and `verilog-auto-arg-sort' to t.

The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
called before and after this function, respectively.

For example:
module ModuleName (/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*AUTOREG*/
InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);

You can also update the AUTOs from the shell using:
emacs --batch <filenames.v> -f verilog-batch-auto
Or fix indentation with:
emacs --batch <filenames.v> -f verilog-batch-indent
Likewise, you can delete or inject AUTOs with:
emacs --batch <filenames.v> -f verilog-batch-delete-auto
emacs --batch <filenames.v> -f verilog-batch-inject-auto
Or check if AUTOs have the same expansion
emacs --batch <filenames.v> -f verilog-batch-diff-auto

Using C-h f, see also:
`verilog-auto-arg' for AUTOARG module instantiations
`verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
`verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
`verilog-auto-inout' for AUTOINOUT making hierarchy inouts
`verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
`verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
`verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
`verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
`verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
`verilog-auto-input' for AUTOINPUT making hierarchy inputs
`verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
`verilog-auto-insert-last' for AUTOINSERTLAST insert code from lisp function
`verilog-auto-inst' for AUTOINST instantiation pins
`verilog-auto-star' for AUTOINST .* SystemVerilog pins
`verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
`verilog-auto-logic' for AUTOLOGIC declaring logic signals
`verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
`verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
`verilog-auto-reg' for AUTOREG registers
`verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
`verilog-auto-reset' for AUTORESET flop resets
`verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
`verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
`verilog-auto-undef' for AUTOUNDEF `undef of local `defines
`verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
`verilog-auto-wire' for AUTOWIRE instantiation wires

`verilog-read-defines' for reading `define values
`verilog-read-includes' for reading `includes

If you have bugs with these autos, please file an issue at
URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
Wilson Snyder (wsnyder@wsnyder.org).