verilog-auto-wire

verilog-auto-wire is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-wire)

Expand AUTOWIRE statements, as part of M-x verilog-auto.
Make wire statements for instantiations outputs that aren't
already declared. `verilog-auto-wire-type' may be used to change
the datatype of the declarations.

Limitations:
This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
and all buses must have widths, such as those from AUTOINST, or using []
in AUTO_TEMPLATEs.

This does NOT work on memories or SystemVerilog .name connections,
declare those yourself.

Verilog mode will add "Couldn't Merge" comments to signals it cannot
determine how to bus together. This occurs when you have ports with
non-numeric or non-sequential bus subscripts. If Verilog mode
mis-guessed, you'll have to declare them yourself.

An example (see `verilog-auto-inst' for what else is going on here):

module ExampWire (o,i);
output o;
input i;
/*AUTOWIRE*/
InstModule instName
(/*AUTOINST*/);
endmodule

Typing M-x verilog-auto will make this into:

module ExampWire (o,i);
output o;
input i;
/*AUTOWIRE*/
// Beginning of automatic wires
wire [31:0] ov; // From inst of inst.v
// End of automatics
InstModule instName
(/*AUTOINST*/
// Outputs
.ov (ov[31:0]),
// Inputs
.i (i));
wire o = | ov;
endmodule