verilog-auto-tieoff

verilog-auto-tieoff is an interactive compiled Lisp function in `verilog-mode.el'.


(verilog-auto-tieoff)

Expand AUTOTIEOFF statements, as part of M-x verilog-auto.
Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
signals to deasserted.

/*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
input/output list as another module, but no internals. Specifically, it
finds all outputs in the module, and if that input is not otherwise declared
as a register or wire, creates a tieoff.

AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match `verilog-active-low-regexp' will be deasserted by tying
them to a one.

You can add signals you do not want included in AUTOTIEOFF with
`verilog-auto-tieoff-ignore-regexp'.

`verilog-auto-wire-type' may be used to change the datatype of
the declarations.

`verilog-auto-reset-widths' may be used to change how the tieoff
value's width is generated.

An example of making a stub for another module:

module ExampStub (/*AUTOINST*/);
/*AUTOINOUTPARAM("Foo")*/
/*AUTOINOUTMODULE("Foo")*/
/*AUTOTIEOFF*/
// verilator lint_off UNUSED
wire _unused_ok = &{1'b0,
/*AUTOUNUSED*/
1'b0};
// verilator lint_on UNUSED
endmodule

Typing M-x verilog-auto will make this into:

module ExampStub (/*AUTOINST*/...);
/*AUTOINOUTPARAM("Foo")*/
/*AUTOINOUTMODULE("Foo")*/
// Beginning of autotieoff
output [2:0] foo;
// End of automatics

/*AUTOTIEOFF*/
// Beginning of autotieoff
wire [2:0] foo = 3'b0;
// End of automatics
...
endmodule