verilog-auto-reg

verilog-auto-reg is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-reg)

Expand AUTOREG statements, as part of M-x verilog-auto.
Make reg statements for any output that isn't already declared,
and isn't a wire output from a block. `verilog-auto-wire-type'
may be used to change the datatype of the declarations.

Limitations:
This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').

This does NOT work on memories, declare those yourself.

An example:

module ExampReg (o,i);
output o;
input i;
/*AUTOREG*/
always o = i;
endmodule

Typing M-x verilog-auto will make this into:

module ExampReg (o,i);
output o;
input i;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg o;
// End of automatics
always o = i;
endmodule