verilog-auto-reg-input

verilog-auto-reg-input is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-reg-input)

Expand AUTOREGINPUT statements, as part of M-x verilog-auto.
Make reg statements instantiation inputs that aren't already declared.
This is useful for making a top level shell for testing the module that is
to be instantiated.

Limitations:
This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').

This does NOT work on memories, declare those yourself.

An example (see `verilog-auto-inst' for what else is going on here):

module ExampRegInput (o,i);
output o;
input i;
/*AUTOREGINPUT*/
InstModule instName
(/*AUTOINST*/);
endmodule

Typing M-x verilog-auto will make this into:

module ExampRegInput (o,i);
output o;
input i;
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared ...
reg [31:0] iv; // From inst of inst.v
// End of automatics
InstModule instName
(/*AUTOINST*/
// Outputs
.o (o[31:0]),
// Inputs
.iv (iv));
endmodule