verilog-auto-output

verilog-auto-output is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-output)

Expand AUTOOUTPUT statements, as part of M-x verilog-auto.
Make output statements for any output signal from an /*AUTOINST*/ that
isn't an input to another AUTOINST. This is useful for modules which
only instantiate other modules.

Limitations:
This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').

If placed inside the parenthesis of a module declaration, it creates
Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).

Typedefs must match `verilog-typedef-regexp', which is disabled by default.

Types are added to declarations if an AUTOLOGIC or
`verilog-auto-wire-type' is set to logic.

Signals matching `verilog-auto-output-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

module ExampOutput (ov,i);
input i;
/*AUTOOUTPUT*/
InstModule instName
(/*AUTOINST*/);
endmodule

Typing M-x verilog-auto will make this into:

module ExampOutput (ov,i);
input i;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] ov; // From inst of inst.v
// End of automatics
InstModule instName
(/*AUTOINST*/
// Outputs
.ov (ov[31:0]),
// Inputs
.i (i));
endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting outputs starting with ov:

/*AUTOOUTPUT("^ov")*/