verilog-auto-output-every

verilog-auto-output-every is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-output-every)

Expand AUTOOUTPUTEVERY statements, as part of M-x verilog-auto.
Make output statements for any signals that aren't primary inputs or
outputs already. This makes every signal in the design an output. This is
useful to get Synopsys to preserve every signal in the design, since it
won't optimize away the outputs.

An example:

module ExampOutputEvery (o,i,tempa,tempb);
output o;
input i;
/*AUTOOUTPUTEVERY*/
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule

Typing M-x verilog-auto will make this into:

module ExampOutputEvery (o,i,tempa,tempb);
output o;
input i;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output tempb;
output tempa;
// End of automatics
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting outputs starting with ov:

/*AUTOOUTPUTEVERY("^ov")*/