verilog-auto-inout-modport

verilog-auto-inout-modport is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-inout-modport)

Expand AUTOINOUTMODPORT statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified interface
and modport and insert into the current module. This is useful
for making verification modules that connect to UVM interfaces.

The first parameter is the name of an interface.

The second parameter is a regexp of modports to read from in
that interface.

The optional third parameter is a regular expression, and only
signals matching the regular expression will be included.

Limitations:
If placed inside the parenthesis of a module declaration, it creates
Verilog 2001 style, else uses Verilog 1995 style.

Interface names must be resolvable to filenames. See `verilog-auto-inst'.

As with other autos, any inputs/outputs declared in the module
will suppress the AUTO from redeclaring an inputs/outputs by
the same name.

An example:

interface ExampIf
( input logic clk );
logic req_val;
logic [7:0] req_dat;
clocking mon_clkblk @(posedge clk);
input req_val;
input req_dat;
endclocking
modport mp(clocking mon_clkblk);
endinterface

module ExampMain
( input clk,
/*AUTOINOUTMODPORT("ExampIf" "mp")*/
// Beginning of automatic in/out/inouts (from modport)
input [7:0] req_dat,
input req_val
// End of automatics
);
/*AUTOASSIGNMODPORT("ExampIf" "mp")*/
endmodule

Typing M-x verilog-auto will make this into:

...
module ExampMain
( input clk,
/*AUTOINOUTMODPORT("ExampIf" "mp")*/
// Beginning of automatic in/out/inouts (from modport)
input req_dat,
input req_val
// End of automatics
);

If the modport is part of a UVM monitor/driver class, this
creates a wrapper module that may be used to instantiate the
driver/monitor using AUTOINST in the testbench.