verilog-auto-inout-in

verilog-auto-inout-in is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-inout-in)

Expand AUTOINOUTIN statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified module and
insert them as all inputs into the current module. This is
useful for making monitor modules which need to see all signals
as inputs based on another module. Any I/O which are already
defined in this module will not be redefined. See also
`verilog-auto-inout-module'.

Limitations:
If placed inside the parenthesis of a module declaration, it creates
Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames. See `verilog-auto-inst'.

Signals are not inserted in the same order as in the original module,
though they will appear to be in the same order to an AUTOINST
instantiating either module.

An example:

module ExampShell (/*AUTOARG*/);
/*AUTOINOUTIN("ExampMain")*/
endmodule

module ExampMain (i,o,io);
input i;
output o;
inout io;
endmodule

Typing M-x verilog-auto will make this into:

module ExampShell (/*AUTOARG*/i,o,io);
/*AUTOINOUTIN("ExampMain")*/
// Beginning of automatic in/out/inouts (from specific module)
input i;
input io;
input o;
// End of automatics
endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:

/*AUTOINOUTIN("ExampMain","^i")*/