verilog-auto-assign-modport

verilog-auto-assign-modport is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-assign-modport)

Expand AUTOASSIGNMODPORT statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified interface
and modport and use to build assignments into the modport, for
making verification modules that connect to UVM interfaces.

The first parameter is the name of an interface.

The second parameter is a regexp of modports to read from in
that interface.

The third parameter is the instance name to use to dot reference into.

The optional fourth parameter is a regular expression, and only
signals matching the regular expression will be included.

Limitations:

Interface names must be resolvable to filenames. See `verilog-auto-inst'.

Inouts are not supported, as assignments must be unidirectional.

If a signal is part of the interface header and in both a
modport and the interface itself, it will not be listed. (As
this would result in a syntax error when the connections are
made.)

See the example in `verilog-auto-inout-modport'.