verilog-auto-arg

verilog-auto-arg is a compiled Lisp function in `verilog-mode.el'.

(verilog-auto-arg)

Expand AUTOARG statements.
Replace the argument declarations at the beginning of the
module with ones automatically derived from input and output
statements. This can be dangerous if the module is instantiated
using position-based connections, so use only name-based when
instantiating the resulting module. Long lines are split based
on the `fill-column', see C-x f.

Limitations:
Concatenation and outputting partial buses is not supported.

Typedefs must match `verilog-typedef-regexp', which is disabled by default.

For example:

module ExampArg (/*AUTOARG*/);
input i;
output o;
endmodule

Typing M-x verilog-auto will make this into:

module ExampArg (/*AUTOARG*/
// Outputs
o,
// Inputs
i
);
input i;
output o;
endmodule

The argument declarations may be printed in declaration order to
best suit order based instantiations, or alphabetically, based on
the `verilog-auto-arg-sort' variable.

Formatting is controlled with `verilog-auto-arg-format' variable.

Any ports declared between the ( and /*AUTOARG*/ are presumed to be
predeclared and are not redeclared by AUTOARG. AUTOARG will make a
conservative guess on adding a comma for the first signal, if you have
any ifdefs or complicated expressions before the AUTOARG you will need
to choose the comma yourself.

Avoid declaring ports manually, as it makes code harder to maintain.