verilog-cpp-keywords

verilog-cpp-keywords is a variable defined in `verilog-mode.el'.
Its value is

("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else" "endif")

Documentation:
Keywords to complete when at first word of a line in declarative scope.
(initial, always, begin, assign...)
The procedures and variables defined within the Verilog program
will be completed at runtime and should not be added to this list.